1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and in particular, to a non-volatile semiconductor memory device which has a high access rate to a non-defective sector.
2. Description of the Related Art
Referring to FIG. 7, a conventional non-volatile semiconductor memory device 300 includes a redundant circuit 310, a row decoder 320, a word line driver 330, a memory cell array 340, and a read/write circuit 350.
The memory cell array 340 is composed of a redundant area 341, a data area 342, a management (domain) area 343, and a redundant area 344. The redundant area 341 includes a non-defective sector as an alternative to a defective sector of a plurality of row sectors arranged in a row direction of the data area 342. The row sector means a xe2x80x9cblockxe2x80x9d comprising a plurality of memory cells connected to one word line among a plurality of word lines arranged in a row direction of the data area 342. The data area 342 includes a plurality of memory cell which are arranged like an array in a row direction and a column direction.
The management area 343 holds information as to which of the plurality of sectors of the data area 342 is a defective sector. The redundant area 344 includes a non-defective sector as an alternative to a defective sector of a plurality of column sectors arrayed in a column direction of the data area 342. The column sector means a xe2x80x9cblockxe2x80x9d comprising a plurality of memory cells connected to one bit line of a plurality of bit lines arranged in a column direction of the data area 342.
When a row sector of the data area 342 designated by a row address decoding a row address signal is a defective sector, the redundant circuit 310 selects a non-defective sector from the redundant area 341 as an alternative to the defective sector.
The row decoder 320 decodes a row address signal inputted from an external element, and then, outputs the decoded row address to the redundant circuit 310 and the word line driver 330.
The word line driver 330 activates a row sector designated by the row address from the row decoder 320. Further, the word line driver 330 selects a non-defective sector from the redundant area 341 as an alternative to the defective sector of the data area 342 on the basis of a selecting signal from the redundant circuit 310.
The read/write circuit 350 reads and writes a data to a memory cell designated by a word line and a bit line.
Referring now to FIG. 8, the redundant circuit 310 is composed of spare decoders 311 and 312, and an AND gate 313. FIG. 8 shows the case where two non-defective sectors 3411 and 3412 is included in the redundant area 341. The spare decoders 311 and 312 decode address signals X0 to Xn, and then, when the decoded row address is a defective sector, inactivates all of a plurality of the sectors included in the data area 342 while outputting an L (logical low) level or H (logical high) level signal in order to activate a non-defective sector of the redundant area 341 as an alternative to the defective sector. For example, when selecting the non-defective sector 3411, the spare decoder 311 outputs an L level signal; on the other hand, the spare decoder 312 outputs an H level signal. In this case, these spare decoders 311 and 312 output an H level signal when a sector designated by the address signals X0 to Xn is a non-defective sector.
The AND gate 313 operates a logical product of the L level signal or H level signal outputted from the spare decoders 311 and 312.
The row decoder 320 includes NAND gates 321 to 32n and inverters 351 to 35n. These inverters 351 to 35n invert the address signals X0 to Xn, respectively. Each of the NAND gates 321 to 32n operates a logical product of an output signal of the AND gate 313 and a logical product of two signals selected from the address signals X0 to Xn and /X0 to /Xn, and then, outputs an inverted signal of the operation result.
The word line driver 330 includes inverters 328, 329 and 331 to 33n. The inverters 328 and 329 receive output signals from the spare decoders 311 and 312, and then, selectively activate two non-defective sectors 3411 and 3412 included in the redundant circuit 341. Moreover, Each of inverters 331 to 33n receives each output signal from the NAND gates 321 to 32n, and then, selectively activates a sector of the corresponding data area 342.
The memory cell 340 includes a plurality of memory cells which are arranged like an array of m row x n column.
When the memory cell 3421 of the data area 342 is defective, a sector 3422 becomes a defective sector. Therefore, when address signals X0 to Xn and /X0 to /Xn designating the defective sector 3422 are inputted, the spare decoders 311 and 312 output a signal for selecting the sector 3411 of the redundant area 341 as an alternative to the defective sector 3422. More specifically, the spare decoder 311 outputs an L level signal; on the other hand, the spared decoder 312 outputs an H level signal.
Whereupon the AND gate 313 outputs an L level signal to the NAND gates 321 to 32n of the row decoder 320. Each of the NAND gates 321 to 32n necessarily outputs an H level signal because an L level signal is inputted from the AND gate 313 although two H level signals are inputted for designating a sector from the address signals X0 to Xn and /X0 to /Xn. Each of inverters 331 to 33n of the word line driver 330 receives an H level signal from the NAND gates 321 to 32n, and then, outputs an L level signal so as to activate the corresponding sector. Namely, when the address signals X0 to Xn and /X0 to /Xn designating the defective sector 3422 are inputted, all sectors of the data area 342 are inactivated.
On the other hand, the inverter 328 of the word line driver 330 receives an L level signal from the spare decoder 311, and then, outputs an H level signal so as to activate the non-defective sector 3411. Moreover, the inverter 329 receives an H level signal from the spare decoder 312, and then, outputs an L level signal so as to inactivate the non-defective sector 3412. By doing so, a non-defective sector 3412 of the redundant area 341 is selected as an alternative to the defective sector 3422 of the data area 342. Then, a bit line corresponding to a column address decoded by a column decoder (not shown) is activated, and then, the read/write circuit 50 writes, reads and erases a data to each of n memory cells connected to the non-defective sector 3411.
In the non-volatile semiconductor memory device 300, as shown in FIG. 9, the data area 342 is divided into blocks BLK1 to BLKr including a predetermined number of row sectors, and then, write, read and erase of data are carried out using blocks BLK1 to BLKr as a management unit. Each of blocks BLK1 to BLKr includes 8 sectors, for example.
The above method of using the blocks BLK1 to BLKr as a management unit is called as an MGM (Mostly Good Memory) method. This MGM method is a method of making usable non-volatile semiconductor memory device even if all of blocks BLK1 to BLKr are not composed of a non-defective sector. More specifically, according to the MGM method, the non-volatile semiconductor memory device is usable in a manner that even if a defective sector is included in one block, an access is made to a non-defective sector as an alternative to the defective sector. Namely, as described above, the non-volatile semiconductor memory device is usable in a manner that an access is made to the non-defective sector 3411 of the redundant area 341 as an alternative to the defective sector 3422 of the data area 342.
However, as shown in FIG. 9, in the case where blocks BLK3, BLK6 and BLKr-4 of the data area 342 include a defective sector, according to the aforesaid MGM method, these blocks make a logical arrangement as shown in FIG. 10 in the case of providing a non-defective sector as an alternative to the defective sector. More specifically, this is the same arrangement such that the blocks BLK3, BLK6 and BLKr-4 are provided in the redundant area 341. Because, according to the method of using each of the blocks BLK1 to BLKr as a management unit, no access is made with respect to the blocks BLK3, BLK6 and BLKr-4 including a defective sector; therefore, these blocks BLK3, BLK6 and BLKr-4 are treated as a defective block.
Accordingly, in the case where each of blocks BLK1 to BLKn includes 8 sectors, 24 sectors (=3xc3x978) become a defective sector; for this reason, there is a problem of reducing an MGM rate.
The present invention has been made taking the aforesaid problem in the prior art into consideration. It is, therefore, an object of the present invention to provide a non-volatile semiconductor memory device having a low defective rate.
In order to achieve the above object, the present invention provides a non-volatile semiconductor memory device which executes data write, read and erase using a block including a plurality of sectors having a plurality of memory cells and arranged in a row direction, comprising: a memory cell array having a data area including a plurality of the blocks; a sector selecting circuit inputting a row address signal for designating each of the plurality of sectors included in the data area, selecting an alternate non-defective sector as an alternative to a defective sector when the address signal designates the defective sector, and making no selection of the alternate non-defective sector when the address signal designates the alternate non-defective sector; and a sector activation circuit for activating a sector selected by the sector selecting circuit, and for inactivating a sector which is not selected by the sector selecting circuit, the alternate non-defective sector being provided in at least one block in response to the number of the defective sectors.
In the non-volatile semiconductor memory device of the present invention, data write, read and erase are executed using a block including a plurality of sectors as a unit. In the case of making an access to each of the plurality of sectors included in the data area, when a sector designated by a row address signal is a defective sector, an access is made to an alternate non-defective sector as an alternative to the defective sector, and then, data write, read and erase are executed. Moreover, when the sector designated by the row address signal is an alternate non-defective sector, no selection of the alternate non-defective sector is made. The alternate non-defective sector is provided in response to the number of the defective sectors. In the case where there exist a plurality of the defective sectors, a plurality of alternate non-defective sectors corresponding to the defective sectors are collected to one block. When the number of the alternate non-defective sectors exceeds the number of sectors included in one block, the alternate non-defective sectors are provided in a plurality of blocks.
Therefore, according to the present invention, the defective sectors included in the data area is collected to one place. As a result, it is possible to make high a rate of making an access to a non-defective sector when accessing a sector of the data area.
Preferably, the sector selecting circuit makes no selection with respect to all of a plurality of the sectors when the row address signal designates the alternate non-defective sector.
When the sector designated by the row address signal is an alternate non-defective sector, no selection is made with respect to all of a plurality of sectors included in the data area, and thereby, an access is made to the defective sector as an alternative to the alternate non-defective sector. Namely, no selection is made with respect to all of a plurality of sectors, and thereby, a data xe2x80x9c0xe2x80x9d is outputted; therefore, this means that the defective sector is selected as an alternative to the alternate non-defective sector.
Therefore, according to the present invention, only when the defective sector is designated, the alternate non-defective sector is merely selected as an alternative to the defective sector, and thereby, it is possible to replace the defective sector with the alternate non-defective sector.
Preferably, the data area includes a redundant area comprising at least one block provided with the alternate non-defective sector.
The redundant area provided with the alternate non-defective sector is included in the data area.
Therefore, according to the present invention, an occupied area is made small, and it is possible to make high a probability of making an access to a non-defective sector.
Preferably, the sector selecting circuit includes: a row decoder for decoding the row address signal, and for outputting a decoded row address to the sector activation circuit; and a redundant circuit for outputting a relief signal for making no selection of the defective sector when the row address signal designates the defective sector to the row decoder, for outputting an activation signal for activating the alternate non-defective sector to the sector activation circuit, and for outputting a no selection signal for making no selection of the plurality of sectors when the row address signal designates the alternate non-defective sector.
The row decoder decodes a row address signal, and then, outputs the decoded row address signal to the activation circuit. When a sector designated by the row address signal is a defective sector, the redundant circuit outputs a relief signal to the row decoder so as to make no selection of the defective sector, and outputs an activation signal to the activation circuit so as to activate an alternate non-defective sector as an alternative to the defective sector of no selection. Moreover, when the sector designated by the row address signal is an alternate non-defective sector, the redundant circuit outputs a no-selection signal to the row decoder so as to make no selection with respect to all of a plurality of sectors.
Therefore, according to the present invention, it is possible to make an access to the alternate non-defective sector as an alternative to the defective sector by the redundant circuit.
Preferably, the row decoder includes a plurality of first logic elements which is provided so as to correspond to the plurality of sectors included in the data area, and operates a logical product of the row address signal and the relief signal, and the sector activation circuit includes: at least one second logic element which is provided so as to correspond to the alternate non-defective sector included in the redundant area, and operates a logical product of an output signal from the first logic element and the activation signal; and a plurality of third logic elements which are provided so as to correspond to the plurality of sectors included in the data area with the exception of the redundant area, and inverts the output signal from the first logic element.
The first logic element of the row decoder operates a logical product of the row address signal and the relief signal from the redundant circuit, and then, outputs the operation result to the activation circuit. The second logic element of the activation circuit operates a logical product of an output signal of the row decoder and an activation signal from the redundant circuit, and then, activates the corresponding alternate non-defective sector on the basis of the operation result. Moreover, the third logic element of the activation circuit inverts the output signal of the row decoder so as to activate the corresponding sector.
Therefore, according to the present invention, when the row address signal designates the defective sector of the data area and when the row address signal designates the alternate non-defective sector of the redundant area, the logic of the relief signal and the activation signal is changed, and thereby, it is possible to replace the defective sector with the alternate non-defective sector.
Preferably, the redundant circuit includes a programmable ROM which stores a redundant information indicative that an alternate non-defective sector as an alternative to a defective sector in areas except the redundant area is held in the redundant area.
The redundant circuit includes the programmable ROM which stores and holds a redundant information indicative that which of the plurality of sectors of the data area is a defective sector. When the row address signal is inputted to the sector selecting circuit from the external element, an access is made to the programmable ROM, and then, a decision is made whether or not a sector designated by the row address signal is a defective sector. In the case where the defective sector is designated, an alternate non-defective sector is selected as an alternative to the defective sector; on the other hand, in the case where the alternate non-defective sector is designated, no selection is made with respect to all of the plurality of sectors.
Therefore, according to the present invention, it is possible to accurately make an access to the alternate non-defective sector as an alternative to the defective sector.
Preferably, the programmable ROM of the redundant circuit stores the redundant information by a fuse system.
The redundant circuit determines whether or not the sector designated by the row address signal is a defective sector by making a decision whether or not the fuse is blown.
Therefore, according to the present invention, it is possible to accurately make an access to the alternate non-defective sector as an alternative to the defective sector with a simple configuration.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawing.